`timescale 1 ns / 1 ps
/*------------------- include --------------------*/

/*---------------------------------------------*/

`define CLOCK_FREQ_MHz 50.0   //系统主频 MHz

module tb; 

reg clk ; 

reg rst_n;          //复位信号


//生成时钟
parameter NCLK = 1000/`CLOCK_FREQ_MHz; 
initial begin
	clk=0;
	forever clk=#(NCLK/2) ~clk; 
end 

initial begin
    $dumpfile("wave.vcd");
    $dumpvars(0, tb);   //dumpvars(深度, 实例化模块1，实例化模块2，.....)
end

/*----------------------------- 模块 ------------------------------*/
reg signed [15:0] speed = 0 ;

test_top u_test_top(
    .clk( clk ),
    .rst_n(rst_n) , 
    .o_pwm()
);


//状态监控
integer dlt  = 0 ;
always@ (posedge clk) begin
    if(u_test_top.write_strobe)begin //
        $display("Write 0x%02x: 0x%02x", u_test_top.port_id , u_test_top.out_port ) ;
        // case(u_test_top.port_id)

        //     8'h05:  begin 
        //         $display("-> %d ns | dltTime %d ns: %d freq:%dMHz",$time ,$time - dlt  ,$signed(speed) , `CLOCK_FREQ_MHz) ;
        //         dlt = $time;
        //     end 
        //     8'hFF: begin
        //         $write("%c",u_test_top.out_port) ;
        //     end
        //     8'h0b: begin
        //         $display("%d ns | pwm=%d", $time ,  u_test_top.out_port);
        //     end
        // endcase 
    end 
end  


integer file_handle;
initial begin
    file_handle = $fopen("test.txt", "w");
    if (file_handle != 0) begin
        forever @(posedge clk) begin
            if(u_test_top.write_strobe && u_test_top.port_id==8'h00) begin
                $fwrite(file_handle,"%02xh ",u_test_top.out_port) ;
            end
        end
    end
end

initial begin
    $display(" -------- test_top sim ----------");
    rst_n = 0;
    repeat(2) @(posedge clk) ;
    rst_n = 1 ; 
    repeat(500) @(posedge clk) ;

    $display("%d ns:done",$time);
	$dumpflush;
	$finish;
	$stop;	
end

endmodule
